1. Field of the Invention
The present invention relates to an apparatus for adjusting finely the input capacitance of a semiconductor device without increasing a layout area of the device, and to a method of fabricating the apparatus.
2. Discussion of the Related Art
FIG. 1 illustrates a block diagram of an input part 5 of a semiconductor memory device according to a related art. As shown in FIG. 1, the input part 5 includes an input pad 10 for transmitting an input signal IN as a signal A, an Electro-Static Discharge (ESD) protection circuit 20 for limiting a passage of ESD as it transmits the signal A to protect the internal circuitry of the memory device, an input buffer 30 for outputting a signal B by converting the level of an output signal of the ESD protection circuit 20 into an appropriate internal logic level of the memory device, and a controller & memory cell array 40 for producing an internal operation signal OUT based on the output signal B of the input buffer 30. These components of the input part 5 are implemented on a chip.
FIG. 2 illustrates a detailed circuit diagram of the ESD protection circuit 20 and the input buffer 30 shown in FIG. 1. As shown in FIG. 2, the ESD protection circuit 20 is constructed with a resistor R1 connected between an input node Nd1 and an output node Nd2, and an NMOS type transistor N1 connected between the output node Nd2 and a ground voltage Vss. As the drain and the gate of the transistor N1 are connected together, the transistor N1 acts as a diode. The input node Nd1 receives the output signal A of the input pad 10. The input buffer 30 includes a buffer 32 connected between the output node Nd2 and the controller and memory cell array 40 for generating and outputting the signal B to the controller & memory cell array 40.
The input capacitance at an input stage of the semiconductor device varies depending on a junction capacitance Cj at a P-N junction of the NMOS transistor N1 of the ESD protection circuit 20 connected to the input stage and depending on a gate capacitance Cg of the input buffer 30 connected to the input stage. Since the input capacitance affects the operation of the semiconductor device, the ESD protection circuit 20 and input buffer 30 are generally designed to provide a desired input capacitance for the semiconductor device.
However, even if all the input parts have been designed to provide the desired input capacitance for the semiconductor device, the input capacitance considered outside a chip is different in accordance with input pins which thwarts this effort for obtaining the desired input capacitance. Due to the length difference in a lead-frame and a bonding wire between the input pins in a semiconductor package, input capacitance varies from 7 to 10% depending on the input pins. This causes a significant difference between the operational characteristics of different input pins, which degrades the operation and performance of the semiconductor device.
To overcome this problem, a circuit for adjusting the input capacitance of the input pins has been proposed. However, in this case, the layout area of the semiconductor device is increased due to the addition of this new circuit. This increases the overall size of the semiconductor device. Therefore, there is a need for an apparatus for adjusting the input capacitance of the semiconductor device without requiring an additional layout area.